This invention relates generally to power semiconductor devices, and more particularly the invention relates to a power semiconductor rectifier device and a method of making same.
Power semiconductor rectifiers have a variety of applications including use in power supplies and power converters. Heretofore, Schottky diodes have been used in these applications. A Schottky diode is characterized by a low turn on voltage, fast turn off, and nonconductance when the diode is reverse biased. However, to create a Schottky diode a metal-silicon barrier must be formed. In order to obtain proper characteristics for the Schottky diode, the barrier metal is likely different than the metal used in other process tips such as metal ohmic contacts. Further, Schottky diode rectifiers suffer from problems such as high leakage current and reverse power dissipation. Also, these problems increase with temperature thus causing reliability problems for power supply applications. Therefore the design the voltage converters using Schottky barrier diodes can cause design problems for many applications.
A semiconductor power rectifier device is known which does not employ Schottky diodes. FIG. 1 from U.S. Pat. No. 5,818,084 is a schematic of such a device which comprises a MOSFET transistor shown generally at 10 having a source/drain 12 which is shorted to a gate 14. A parasitic diode 16 is connected from the source/drain 12 to the drain/source 18. The patent discloses the use of a trench for accommodating the gate.
U.S. Pat. No. 6,186,408, supra, discloses a vertical semiconductor power rectifier device which employs a large number of parallel connected cells, each cell comprising a MOSFET structure with a gate-drain short via common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the device. The method of manufacturing the rectifier device provides highly repeatable device characteristics and reduced manufacturing costs. The active channel regions of the device are defined using pedestals in a double spacer, double implant self-aligned process. The channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations and spatial sidewall formation.
The co-pending applications identified above disclose improved methods of manufacturing a semiconductor power rectifier device and resulting structure. As shown in the section view of FIG. 2, the semiconductor substrate 20 including epitaxial layer 22 function as one source/drain (e.g., the drain) of the device. A plurality of second source/drains (e.g., source) regions 24 are formed on a major surface of the substrate along with a plurality of gate electrodes 26 and the source/drains 24 and gate electrodes 26 positioned within a guard ring 28, along with, optionally, conductive plugs 30 in the major surface. A conductive layer 32 contacts source/drain regions 24 and gate electrodes 26, and conductive layer 34 contacts substrate 20.
The semiconductor rectifier device is fabricated using conventional semiconductor processing steps including photoresist masking, plasma etching, and ion implantation in forming the guard ring, connective plug, source/drain regions, and gate electrodes overlying device channel regions. In accordance with one feature of the disclosed process, a photoresist mask is used in defining the gate oxide and gate of the device, which is anisotropically or otherwise etched to expose peripheral portions of the gate electrode through which ions are implanted to create channel regions in body regions under and controlled by the gate electrode. FIG. 3 is a plan view of the device showing in the boundary of substrate 20, guard ring 28, optional plugs 30, gate regions 26 and source/drains 24 which are in between gate regions 26, and top electrode 32. The P/N junction 36 between the channel region and the epitaxial layer 22 of the bottom source/drain is defined by shallow uniform boron implant which forms P region 38.
The devices disclosed in the above patent and co-pending patent applications realize a low Vf by having short channel regions under the gate structures. However, the reverse bias leakage current of an MOS diode may increase when Vf is very low due to the nature of short channel MOS transistors.
The present invention is directed to utilizing a longer channel region under the controlled gate in order to limit reverse bias current leakage.